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| M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers description the M37920S4CGP is a single-chip microcomputers designed with high-performance cmos silicon gate technology. these are housed in 100-pin plastic molded qfp. this microcomputer supports the 7900 series instruction set, which are enhanced and expanded in- struction set and are upper-compatible with the 7700/7751 series in- struction set. the cpu of this microcomputer is a 16-bit parallel processor that can also be switched to perform 8-bit parallel processing. also, the bus interface unit of this microcomputer enhance the memory access ef- ficiency to execute instructions fast. this microcomputer include the 4-channel dma controller and the dram controller with enhanced fast page mode. therefore, this microcomputer are suitable for of- fice, business, and industrial equipment controller that require fast processing of large data. distinctive features preliminary notice: this is not a final specification. some parametric limits are subject to change. M37920S4CGP 16-bit cmos microcomputer mitsubishi microcomputers 2 block diagram data bank register dt (8) program counter pc (16) incrementer/decrementer (24) program bank register pg (8) input buffer register ib (16) direct page register dpr0 (16) stack pointer s (16) index register y (16) index register x (16) arithmetic logic unit (16) accumulator b (16) accumulator a (16) instruction register (8) central processing unit (cpu) incrementer (24) program address register pa (24) data address register da (24) bus interface unit (biu) reset md1 reference voltage input v ref (0 v) av ss avcc vcc external data bus width select input byte clock generating circuit clock input x in x out data buffer dq 0 (8) instruction queue buffer q 0 (8) data bus (odd) address bus a-d converter (10) watchdog timer timer tb1 (16) timer tb2 (16) timer tb0 (16) timer ta1 (16) timer ta2 (16) timer ta3 (16) timer ta4 (16) timer ta0 (16) input/output port p8 input/output port p7 input/output port p4 input/output port p6 input/output port p5 data bus input/output port p2 input/output port p3 md0 (0 v) vss processor status register ps (11) nmi data bus (even) data buffer dq 1 (8) data buffer dq 2 (8) data buffer dq 3 (8) instruction queue buffer q 1 (8) instruction queue buffer q 2 (8) instruction queue buffer q 3 (8) instruction queue buffer q 4 (8) instruction queue buffer q 5 (8) instruction queue buffer q 6 (8) instruction queue buffer q 7 (8) instruction queue buffer q 8 (8) instruction queue buffer q 9 (8) direct page register dpr1 (16) direct page register dpr2 (16) direct page register dpr3 (16) clock output reset input uart1(9) uart0(9) ram 2048 bytes p8(7) p7(4) p9(7) p4(5) p6(7) p5(8) dram controoler dma0(16) dma1(16) dma2(16) dma3(16) p12(3) data i/o circuit p2(8) p3(2) input/output port p9 input/output port p12 rd read output blw write output (0 v) (5 v) address output circuit address bus 3 M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers rom ram p2, p5 p3 p4 p6, p8 p7 p9 p12 ta0Cta4 tb0Ctb2 uart0 and uart1 memory expansion operating temperature range device structure package number of basic machine instructions instruction execution time external clock input frequency f(x in ) memory size programmable input/output ports multi-functional timers serial i/o a-d converter watchdog timer dma controller dram controller chip-select wait control real-time output interrupts clock generating circuit power supply voltage power dissipation ports input/output characteristics functions (microcomputer mode) functions parameter input/output withstand voltage output current 203 50 ns (the fastest instruction at f(x in ) = 20 mhz) 20 mhz (max.) external 2048 bytes 8-bit 5 2 2-bit 5 1 5-bit 5 1 7-bit 5 2 4-bit 5 1 6-bit 5 1 3-bit 5 1 16-bit 5 5 16-bit 5 3 (uart or clock synchronous serial i/o) 5 2 10-bit successive approximation method 5 1 (4 channels) 12-bit 5 1 4 channels maximum transfer rate 20 mbytes/sec. (at f(x in ) = 20 mhz, 0 wait, 1-bus cycle transfer) 10 mbytes/sec. (at f(x in ) = 20 mhz, 0 wait, 2-bus cycles transfer) 1 channel supports fast page access mode. incorporates 8-bit refresh timer. supports cas before ras refresh method or self refresh method. chip select area 5 4 (cs 0 Ccs 3 ). a wait number and bus width can be set for each chip select area. 4 bits 5 2 channels; or 6 bits 5 1 channel + 2 bits 5 1 channel 6 external types, 17 internal types. each interrupt except nmi can be set to a priority level within the range of 0C7 by software. built-in (externally connected to a ceramic resonator or quartz crystal resonator). 5 v10 % 135 mw (at f(x in ) = 20 mhz, typ.) 5 v 5 ma up to 16 mbytes. note that bank ff 16 is a reserved area. C20 to 85 c cmos high-performance silicon gate process 100-pin plastic molded qfp preliminary notice: this is not a final specification. some parametric limits are subject to change. M37920S4CGP 16-bit cmos microcomputer mitsubishi microcomputers 4 vcc, vss md0 md1 reset x in x out byte avcc, avss v ref a 0 Ca 7 a 8 Ca 15 / ma 0 Cma 7 a 16 Ca 23 / ma 8 Cma 11 d 0 Cd 7 p2 0 /d 8 C p2 7 /d 15 p3 0 /rdy, rd, blw, p3 3 /bhw p4 0 /ale, p4 1 / f 1 , p4 2 /tc, p4 3 /hold, p4 4 /hlda p5 0 Cp5 7 p6 0 Cp6 6 power supply input md0 md1 reset input clock input clock output external data bus width select input analog power supply input reference voltage input low-order address middle-order address/ dram address high-order address/ dram address low-order data i/o port p2/ high-order data memory control signal i/o i/o port p4 i/o port p5 i/o port p6 input input input input output input input output output output i/o i/o input output output output output output i/o input output i/o i/o apply 5 v10 % to vcc, and 0 v to vss. this pin controls the processor mode. connect this pin to v cc . connect this pin to vss. the microcomputer is reset when l level is applies to this pin. these are input and output pins of the internal clock generating circuit. connect a ceramic or quartz- crystal resonator between the x in and x out pins. when an external clock is used, the clock source should be connected to the x in pin, and the x out pin should be left open. this pin determines whether the external data bus has an 8-bit width or 16-bit width for the memory expansion mode or microprocessor mode. the width is 16 bits when l signal is input, and 8 bits when h signal is input. power supply input pin for the a-d converter. connect avcc to vcc, and avss to vss externally. this is the reference voltage input pin for the a-d converter. the low-order 8 bits of address (a 0 Ca 7 ) are output. the middle-order 8 bits of address (a 8 Ca 15 ) are input/output. while dram space is accessed, multiplexed address (ma 0 Cma 7 ) is output. the high-order 8 bits of address (a 16 Ca 23 ) are output. while dram space is ac- cessed, multiplexed address (ma 8 Cma 11 ) is output. the low-order 8 bits of data (d 0 Cd 7 ) are input/output. n when 8-bit external data bus is used (byte = h level) port p2 is an 8-bit i/o port. n when 16-bit external data bus is used (byte = l level) the high-order 8 bits (d 8 Cd 15 ) are input/output. while the input level at pin rdy is l, the microcomputer is placed in the ready state. while pin rd is at l level, the microcomputer reads out data and instruc- tion codes. also, pin rdy can function as a programmable i/o port pin (p3 0 ) by software. n when 8-bit external data bus is used (byte = h level) while pin blw is at l level, the microcomputer writes data. n when 16-bit external data bus is used (byte = l level) while pin blw is at l level, the microcomputer writes data into an even- numbered address. while pin bhw is at l level, the microcomputer writes data into an odd- numbered address. signal ale is used to latch an address. f 1 has the same period as internal clock f . pin p4 2 functions as a programmable i/o port pin. while the input level at pin hold is at l level, the microcomputer is placed in the hold state. signal hlda is used to inform the external that the microcomputer enters the hold state. by software, pin ale, clock f 1 output pin, and pins hold, hlda function as programmable i/o port pins (p4 0 , p4 1 , p4 3 , p4 4 ). pin p4 2 also functions as pin tc. port p5 is an 8-bit i/o port. these pins also function as i/o pins for timers a0, a2, and pulse output pins for the real-time output. port p6 is a 7-bit i/o port. these pins also function as i/o pins for timers a1, a3, a4, input pins for dma requests, and output pins for dma acknowledge signals. pin description (microcomputer mode) functions input/ output name pin 5 M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers i/o i/o output i/o i/o input functions input/ output name pin p7 0 Cp7 3 p8 0 Cp8 6 cs 0 p9 1 Cp9 6 p12 0 Cp12 2 nmi port p7 is a 4-bit i/o port. p7 2 and p7 3 also function as input pins for int 3 and int 4 . according to the software setting, these pins also function as input pins for the a-d converter. port p8 is a 7-bit i/o port. these pins also function as i/o pins for uart0, uart1. this is an output pin for cs 0 . port p9 is a 6-bit i/o port. according to the software setting, p9 1 Cp9 3 also funtion as chip select output pins. while dram space is selected, p9 4 Cp9 6 function as output pins for dram control signals. port p12 is a 3-bit i/o port. these pins also functions as input pins for int 0 , int 1 , int 2 . according to software setting, these pins also function as input pins for timers b0Cb2. this pin is for a non-maskable interrupt. i/o port p7 i/o port p8 chip-select output i/o port p9 i/o port p12 non-maskable interrupt preliminary notice: this is not a final specification. some parametric limits are subject to change. M37920S4CGP 16-bit cmos microcomputer mitsubishi microcomputers 6 fig. 1 memory map int 4 a-d conversion reserved area (note 1) reserved area (note 1) reserved area (note 1) address matching detect dma0 dma1 dma2 dma3 uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 interrupt vector table timer a4 timer a3 timer a2 timer a1 timer a0 watchdog timer brk instruction (note 2) zero divide int 3 int 2 int 1 int 0 nmi reset dbc (note 2) 000000 16 bank 0 16 ffffff 16 fe0000 16 00ffff 16 010000 16 01ffff 16 bank fe 16 000000 16 000800 16 0000ff 16 00fffe 16 00ffc0 16 internal ram 2048 bytes peripheral devices control registers 000fff 16 001000 16 feffff 16 ff0000 16 00ffff 16 00ffc0 16 bank 1 16 bank ff 16 notes 1: do not write to this address. 2: these are interrupts used only for debugging. do not use these interrupts. basic function blocks the M37920S4CGP is the same functions as the m37920f8cgp except for the following. therefore, refer to the datasheet of the m37920f8cgp. ? the M37920S4CGP does not include the internal flash memory. ? the M37920S4CGP operates only in the microprocessor mode. ? the M37920S4CGP does not have the flash memory control regis- ter (address 9e 16 ). ? some of programmable i/o ports of the M37920S4CGP differ from those of the m37920fgcgp. memory figure 1 shows the memory map. 7 M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 2 location of peripheral devices control registers (1) 000000 16 000001 16 000002 16 000003 16 000004 16 000005 16 000006 16 000007 16 000008 16 000009 16 00000a 16 00000b 16 00000c 16 00000d 16 00000e 16 00000f 16 000010 16 000011 16 000012 16 000013 16 000014 16 000015 16 000016 16 000017 16 000018 16 000019 16 00001a 16 00001b 16 00001c 16 00001d 16 00001e 16 00001f 16 000020 16 000021 16 000022 16 000023 16 000024 16 000025 16 000026 16 000027 16 000028 16 000029 16 00002a 16 00002b 16 00002c 16 00002d 16 00002e 16 00002f 16 000030 16 000031 16 000032 16 000033 16 000034 16 000035 16 000036 16 000037 16 000038 16 000039 16 00003a 16 00003b 16 00003c 16 00003d 16 00003e 16 00003f 16 port p2 register port p3 register [port p1 direction register] (note 2) [port p0 direction register] (note 2) [port p1 register] (note 2) [port p0 register] (note 2) port p2 direction register port p3 direction register port p4 register port p5 register port p4 direction register port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register port p8 register port p8 direction register [port p10 register] (note 2) [port p11 register] (note 2) [port p10 direction register] (note 2) [port p11 direction register] (note 2) a-d control register 0 a-d control register 1 a-d register 1 a-d register 2 a-d register 3 uart0 transmit/receive mode register uart0 baud rate register (brg0) uart0 transmit buffer register uart0 transmit/receive control register 1 uart0 receive buffer register uart1 transmit/receive mode register uart1 baud rate register (brg1) uart1 transmit buffer register uart1 transmit/receive control register 0 uart1 transmit/receive control register 1 uart1 receive buffer register address (hexadecimal notation) 000040 16 000041 16 000042 16 000043 16 000044 16 000045 16 000046 16 000047 16 000048 16 000049 16 00004a 16 00004b 16 00004c 16 00004d 16 00004e 16 00004f 16 000050 16 000051 16 000052 16 000053 16 000054 16 000055 16 000056 16 000057 16 000058 16 000059 16 00005a 16 00005b 16 00005c 16 00005d 16 00005e 16 00005f 16 000060 16 000061 16 000062 16 000063 16 000064 16 000065 16 000066 16 000067 16 000068 16 000069 16 00006a 16 00006b 16 00006c 16 00006d 16 00006e 16 00006f 16 000070 16 000071 16 000072 16 000073 16 000074 16 000075 16 000076 16 000077 16 000078 16 000079 16 00007a 16 00007b 16 00007c 16 00007d 16 00007e 16 00007f 16 address (hexadecimal notation) count start register one-shot start register timer a clock division select register timer a0 register timer a1 register timer a2 register timer a3 register timer a4 register timer b0 register timer b1 register timer b2 register timer a1 mode register timer a0 mode register timer a2 mode register timer a3 mode register timer a4 mode register timer b0 mode register timer b1 mode register timer b2 mode register processor mode register 1 watchdog timer register particular function select register 0 particular function select register 1 debug control register 0 int 3 interrupt control register uart0 transmit interrupt control register uart1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b2 interrupt control register int 1 interrupt control register watchdog timer frequency select register debug control register 1 int 4 interrupt control register uart1 transmit interrupt control register timer a2 interrupt control register timer b1 interrupt control register int 2 interrupt control register address comparison register 0 address comparison register 1 particular function select register 2 reserved area (note 1) notes 1: do not read/write to this address. 2: these registers are used in the bus fixation of the power saving function. for details, refer to the section on the power saving function of the m37920f8cgp datasheet. uart0 transmit/receive control register 0 up-down register processor mode register 0 a-d conversion interrupt control register uart0 receive interrupt control register int 0 interrupt control register port p9 register port p9 direction register port p12 register port p12 direction register a-d register 0 reserved area (note 1) reserved area (note 1) preliminary notice: this is not a final specification. some parametric limits are subject to change. M37920S4CGP 16-bit cmos microcomputer mitsubishi microcomputers 8 fig. 3 location of peripheral devices control registers (2) 0000c0 16 0000c1 16 0000c2 16 0000c3 16 0000c4 16 0000c5 16 0000c6 16 0000c7 16 0000c8 16 0000c9 16 0000ca 16 0000cb 16 0000cc 16 0000cd 16 0000ce 16 0000cf 16 0000d0 16 0000d1 16 0000d2 16 0000d3 16 0000d4 16 0000d5 16 0000d6 16 0000d7 16 0000d8 16 0000d9 16 0000da 16 0000db 16 0000dc 16 0000dd 16 0000de 16 0000df 16 0000e0 16 0000e1 16 0000e2 16 0000e3 16 0000e4 16 0000e5 16 0000e6 16 0000e7 16 0000e8 16 0000e9 16 0000ea 16 0000eb 16 0000ec 16 0000ed 16 0000ee 16 0000ef 16 0000f0 16 0000f1 16 0000f2 16 0000f3 16 0000f4 16 0000f5 16 0000f6 16 0000f7 16 0000f8 16 0000f9 16 0000fa 16 0000fb 16 0000fc 16 0000fd 16 0000fe 16 0000ff 16 0000a0 16 0000a1 16 0000a2 16 0000a3 16 0000a4 16 0000a5 16 0000a6 16 0000a7 16 0000a8 16 0000a9 16 0000aa 16 0000ab 16 0000ac 16 0000ad 16 0000ae 16 0000af 16 0000b0 16 0000b1 16 0000b2 16 0000b3 16 0000b4 16 0000b5 16 0000b6 16 0000b7 16 0000b8 16 0000b9 16 0000ba 16 0000bb 16 0000bc 16 0000bd 16 0000be 16 0000bf 16 real-time output control register pulse output data register 0 pulse output data register 1 reserved area (note 1) cts/rts separate select register 000080 16 000081 16 000082 16 000083 16 000084 16 000085 16 000086 16 000087 16 000088 16 000089 16 00008a 16 00008b 16 00008c 16 00008d 16 00008e 16 00008f 16 000090 16 000091 16 000092 16 000093 16 000094 16 000095 16 000096 16 000097 16 000098 16 000099 16 00009a 16 00009b 16 00009c 16 00009d 16 00009e 16 00009f 16 address (hexadecimal notation) cs 0 control register l cs 0 control register h cs 1 control register l cs 1 control register h cs 2 control register l cs 2 control register h cs 3 control register l cs 3 control register h area cs 0 start address register area cs 1 start address register area cs 2 start address register area cs 3 start address register reserved area (note 1) reserved area (note 1) reserved area (note 1) note 1: do not read/write to this address. reserved area (note 1) reserved area (note 1) reserved area (note 1) reserved area (note 1) address (hexadecimal notation) dram control register refresh timer dmac control register l dmac control register h dma0 interruput control register dma1 interruput control register dma2 interruput control register dma3 interruput control register source address register 0 l source address register 0 m source address register 0 h destination address register 0 l destination address register 0 m destination address register 0 h transfer counter register 0 l transfer counter register 0 m transfer counter register 0 h dma0 mode register l dma0 mode register h dma0 control register source address register 1 l source address register 1 m source address register 1 h destination address register 1 l destination address register 1 m destination address register 1 h transfer counter register 1 l transfer counter register 1 m transfer counter register 1 h dma1 mode register l dma1 mode register h dma1 control register source address register 2 l source address register 2 m source address register 2 h destination address register 2 l destination address register 2 m destination address register 2 h transfer counter register 2 l transfer counter register 2 m transfer counter register 2 h dma 2 mode register l dma 2 mode register h dma 2 control register source address register 3 l source address register 3 m source address register 3 h destination address register 3 l destination address register 3 m destination address register 3 h transfer counter register 3 l transfer counter register 3 m transfer counter register 3 h dma 3 mode register l dma 3 mode register h dma 3 control register 9 M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers processor mode the M37920S4CGP operates only in the microprocessor mode ex- clusive for the external rom. be sure to fix the level at pin md0 to vcc and the level at pin md1 to vss. also, be sure to fix bits 1, 0 at address 5e 16 (the processor mode register 0) to 1 and 0, respec- tively. microprocessor mode when the microcomputer starts its operation after reset with the level at pin md0 = vcc level (5 v), the microcomputer is placed in the mi- croprocessor mode. v cc level (5 v) pin md0 after reset, the microcomputer starts its operation in the mi- croprocessor mode. (be sure to pin md0 to vcc level.) processor mode pin md1 v ss level (5 v) table 1. relationship between pins md0, md1 and processor mode preliminary notice: this is not a final specification. some parametric limits are subject to change. M37920S4CGP 16-bit cmos microcomputer mitsubishi microcomputers 10 fig. 4 processor mode register 0s bit configuration 76543210 processor mode register 0 processor mode bits 0 0 : do not select. 0 1 : do not select. 1 0 : microprocessor mode 1 1 : do not select. interrupt priority detection time select bits 0 0 : 7 cycles of f 0 1 : 4 cycles of f 1 0 : 2 cycles of f 1 1 : do not select. software reset bit by a write of ??to this bit, the microcomputer will be reset, and then, restarted. external bus wait number select bits 0 0 : 0 wait 0 1 : 1 wait 1 0 : 2 wait 1 1 : ale expansion wait clock f 1 output select bit 0 : f 1 output is disabled. (p4 1 functions as a programmable i/o port pin.) 1 : f 1 output is enabled. (p4 1 functions as the clock f 1 output pin.) address 5e 16 11 M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 5 processor mode register 1s bit configuration 76543210 processor mode register 1 fix this bit to ?? rdy input select bit 0 : rdy input is disabled. (p3 0 functions as a programmable i/o port pin.) 1 : rdy input is enabled. (p3 0 functions as pin rdy.) ale output select bit 0 : ale output is disabled. (p4 0 functions as a programmable i/o port pin.) 1 : ale output is enabled. (p4 0 functions as pin ale.) direct page register switch bit 0 : only dpr0 is used. 1 : dpr0 to dpr3 are used. recovery cycle insert select bit 0 : no recovery cycle is inserted at access to the external area. 1 : recovery cycle is inserted at access to the external area. address 5f 16 hold input, hlda output select bit 0 : hold input and hlda output are disabled. (p4 0 and p4 4 function as programmable i/o port pins.) 1 : hold input and hlda output are enabled. (p4 3 and p4 4 function as pins hold and hlda, respectively.) ??at read. 00 0 preliminary notice: this is not a final specification. some parametric limits are subject to change. M37920S4CGP 16-bit cmos microcomputer mitsubishi microcomputers 12 fig. 6 microcomputer internal status just after reset (1) 00 00 ( 04 16 ) address port p0 direction register 00 16 ( 05 16 ) port p1 direction register ( 08 16 ) port p2 direction register ( 09 16 ) port p3 direction register ( 15 16 ) port p9 direction register 00 16 ( 0c 16 ) port p4 direction register ( 0d 16 ) port p5 direction register 00 16 ( 10 16 ) port p6 direction register ( 11 16 ) port p7 direction register ( 14 16 ) port p8 direction register ( 56 16 ) timer a0 mode register 00 16 ( 57 16 ) timer a1 mode register 00 16 ( 58 16 ) timer a2 mode register 00 16 ( 59 16 ) timer a3 mode register 00 16 ( 5a 16 ) timer a4 mode register 00 16 ( 18 16 ) port p10 direction register 00 16 ( 19 16 ) port p11 direction register 00 16 notes 1: the contents of the other registers and ram are undefined at reset and must be initialized by software. 2: the status just after reset depends on the voltage level applied to pin md0. 3: at power-on reset, these bits are clear to ?? at hardware or software reset, on the other hand, these bits retain the state just before reset. 0 000 0 ??? ( 1e 16 ) a-d control register 0 0 000 001 ( 1f 16 ) a-d control register 1 1 0 0 000 ( 34 16 ) uart 0 transmit/receive control register 0 1 0 0 000 ( 3c 16 ) uart 1 transmit/receive control register 0 0 000 0 010 ( 35 16 ) uart 0 transmit/receive control register 1 0 000 0 010 ( 3d 16 ) uart 1 transmit/receive control register 1 0 0 000 ( 42 16 ) one-shot start register 00 ( 45 16 ) timer a clock division select register ( 1c 16 ) port p12 direction register ( 30 16 ) uart 0 transmit/receive mode register 00 16 ( 38 16 ) uart 1 transmit/receive mode register 00 16 0 000 0 0 000 ( 44 16 ) up-down register ( 40 16 ) count start register 00 16 0 0? 0 000 ( 5b 16 ) timer b0 mode register 0 0? 0 000 ( 5c 16 ) timer b1 mode register 0 0? 0 000 ( 5d 16 ) timer b2 mode register 1 000 (note 2) 0 (note 2) 0 ( 5e 16 ) processor mode register 0 ( 5f 16 ) processor mode register 1 ( 60 16 ) address watchdog timer (note 3) 0 1 0 0 000 0000 0 fff 16 ( 61 16 ) watchdog timer frequency select register ( 62 16 ) particular function select register 0 ( 63 16 ) particular function select register 1 ( 66 16 ) debug control register 0 ( 67 16 ) debug control register 1 int 2 interrupt control register processor status register ps 00 16 00 16 program bank register pg contents at address ffff 16 program counter pc h contents at address fffe 16 program counter pc l 0000 16 ( 6e 16 ) int 3 interrupt control register ( 6f 16 ) int 4 interrupt control register 0000 ?000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ( 72 16 ) uart 0 receive interrupt control register ( 73 16 ) uart 1 transmit interrupt control register ( 74 16 ) uart 1 receive interrupt control register ( 77 16 ) timer a2 interrupt control register ( 78 16 ) timer a3 interrupt control register ( 79 16 ) timer a4 interrupt control register ( 7a 16 ) timer b0 interrupt control register 0 00 000 ( 7c 16 ) timer b2 interrupt control register 000 ( 7e 16 ) int 1 interrupt control register ( 70 16 ) a-d conversion interrupt control register ( 71 16 ) uart 0 transmit interrupt control register ( 75 16 ) timer a0 interrupt control register ( 76 16 ) timer a1 interrupt control register 0 00 000 ( 7d 16 ) int 0 interrupt control register ( 7b 16 ) timer b1 interrupt control register direct page registers dpr0 to dpr3 ( 7f 16 ) 0 00 1?? 0 00 ?? 0 00 data bank register dt 00 16 00 00 (note 2) 0 000 (note 3) 0000 0 0 000 0 000 000 0000 0 000 000 0 000 000 fff 16 stack pointer 000 (note 3) (note 3) 13 M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 7 microcomputer internal registers status just after reset (2) ( 80 16 ) address cs 0 control register l ( 81 16 ) cs 0 control register h ( 82 16 ) cs 1 control register l ( 83 16 ) cs 1 control register h ( 8c 16 ) area cs 1 start address register ( 84 16 ) cs 2 control register l ( 85 16 ) cs 2 control register h ( 86 16 ) cs 3 control register l ( 87 16 ) cs 3 control register h ( 8a 16 ) area cs 0 start address register ( dc 16 ) dma1 mode register l ( dd 16 ) dma1 mode register h ( de 16 ) dma1 control register ( ec 16 ) dma2 mode register l ( ed 16 ) dma2 mode register h ( 8e 16 ) area cs 2 start address register ( 90 16 ) area cs 3 start address register notes 1: the contents of the other registers and ram are undefined at reset and must be initialized by software. 2: the status just after reset depends on the voltage level applied to pin md0. 3: while vss level voltage is applied to pin byte, these bits are ?? while vcc level voltage is applied to pin byte, on the othe r hand, these bits are ?? 0 000 0 ( a8 16 ) dram control register ( b2 16 ) dma0 interrupt control register 0000 ( b3 16 ) dma1 interrupt control register 0000 ( b4 16 ) dma2 interrupt control register ( cc 16 ) dma0 mode register l 000 ( ce 16 ) dma0 control register ( a0 16 ) real-time output control register ( ac 16 ) cts/rts separate select register ( b0 16 ) dmac control register l 0 0 00 0 000 ( cd 16 ) dma0 mode register h ( b5 16 ) dma3 interrupt control register 0 0 000 ( ee 16 ) dma2 control register ( fc 16 ) dma3 mode register l ( fd 16 ) dma3 mode register h ( fe 16 ) address dma3 control register 0 00 0 0 00 0 000 0 10 (note 2) (note 3) 10 0 100 0 (note 3) 10 0 100 0 (note 3) 10 0 100 0 (note 3) 10 000 0000 0000 0 0 00 0 000 000 0 00 0 0 00 0 000 0 0 00 000 0 001 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 0 000 0 00 0 0 000 0 00 0 0 00 000 0 00 00 0 0 0 0 000 0 0 0 0 0 001 0 000 0 000 000 0 000 0 000 0 000 0 000 0 000 00 ( b1 16 ) dmac control register h 00 preliminary notice: this is not a final specification. some parametric limits are subject to change. M37920S4CGP 16-bit cmos microcomputer mitsubishi microcomputers 14 input/output pins each of ports p3 to p9 and p12 has an direction register, and each bit can be programmed for input or output. a pin becomes an output pin when the corresponding bit of direction register is 1, and an in- put pin when it is 0. when a pin is programmed as an output pin, the data written to its port latch is output to the output pin. when a pin is programmed as an output pin, the contents of the port latch are read out instead of the value of the pin. accordingly, a previously output value can be read out correctly even when the output h voltage is lowered or the output l voltage is raised, owing to an external load, etc. a pin programmed as an input pin is placed in the flooting state, and the value input to the pin can be read out correctly. when a pin is pro- grammed as an input pin, the data can be written only in the port latch, and the pin remains floating. each of figures 8 and 9 shows the block diagram for each port pin. table 2. correspondence between external buses, bus control sig- nals, and programmable i/o port pins external buses, bus control signals a 0 to a 7 , a 8 to a 15 , a 16 to a 23 0 standby state select bit a 0 to a 7 , a 8 to a 15 , a 16 to a 23 1 d 0 to d 7 , d 8 to d 15 (note 1) d 0 to d 7 , d 8 to d 15 p10 0 to p10 7 (note 2) , p11 0 to p11 7 (note 2) , p0 0 to p0 7 (note 2) p1 0 to p1 7 (note 2) , p2 0 to p2 7 rd, blw, bhw rd, blw, bhw (note 1) p3 1 , p3 2 (note 2) , p3 3 cs 0 cs 0 p9 0 (note 2) notes 1: when the external data bus width = 8 bits (byte = v cc level), this becomes a programmable i/o port pin, regardless of the standby state select bit? contents. 2: pin functions of port pins p0, p1, p3 1 , p3 2 , p9 0 , p10, p11 are not shown in the pin configuration. however, relationship with corresponding bus signals and ports is listed in table 2. for the addresses of these port? registers and direction registers, refer to the location of the perpheral devices?control registers (figures 2 and 3). 15 M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 8 block diagram for each port pin (1) [inside dotted-line not included] p2 0 /d 8 to p2 7 /d 15 , p3 3 /bhw [inside dotted-line included] p3 0 /rdy, p4 3 /hold, p6 1 /ta1 in /dmareq 0 , p6 3 /ta3 in /dmareq 1 , p6 5 /ta4 in /dmareq 2 , p6 6 /dmareq 3 , p8 1 /rxd 1 , p8 5 /rxd 0 , p12 0 /int 0 /tb0 in , p12 1 /int 1 /tb1 in , p12 2 /int 2 /tb2 in data bus direction register port latch p4 0 /ale, p4 1 / f 1 , p4 4 /hlda, p6 0 /ta1 out /dmaack 0 , p6 2 /ta3 out /dmaack 1 , p6 4 /ta4 out /dmaack 2 , p8 0 /txd 1 , p8 4 /txd 0 , p9 1 /cs 1 /ras 1 , p9 2 /cs 2 /ras 2 , p9 3 /cs 3 /ras 3 , p9 4 /cas/w, p9 5 /wrl/lcas, p9 6 /wrh/ucas data bus direction register port latch ? output (internal peripheral devices) [inside dotted-line not included] p5 2 /rtp0 2 , p5 3 /rtp0 3 , p5 4 /rtp1 0 , p5 5 /rtp1 1 [inside dotted-line included] p5 1 /ta0 in /rtp0 1 , p5 7 /ta2 in /rtp1 3 data bus direction register port latch latch t q ck timer underflow signal p5 0 /ta0 out /rtp0 0 , p5 6 /ta2 out /rtp1 2 data bus direction register port latch ? latch t q ck timer underflow signal output (internal peripheral devices) preliminary notice: this is not a final specification. some parametric limits are subject to change. M37920S4CGP 16-bit cmos microcomputer mitsubishi microcomputers 16 [inside dotted-line not included] p7 0 /an 0 , p7 1 /an 1 [inside dotted-line included] p7 2 /an 2 /int 3 , p7 3 /an 3 /ad trg /int 4 data bus direction register port latch analog input p8 2 /cts 0 /clk 1 , p8 3 /cts 0 /rts 0 , p8 6 /clk 0 data bus direction register port latch ? ? output (internal peripheral devices) p4 2 /tc data bus direction register port latch ? output (tc) fig. 9 block diagram for each port pin (2) rd, blw, cs 0 , a 0 to a 23 , d 0 to d 7 data bus direction register port latch ? output (internal peripheral devices) 17 M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers absolute maximum ratings recommended operating conditions (vcc = 5 v, ta = C20 to 85 c, unless otherwise noted) unit v v v v mw c c parameter power source voltage analog power source voltage input voltage d 0 Cd 7 , d 8 /p2 0 Cd 15 /p2 7 , p3 0 , p3 3 , p4 0 Cp4 4 , p5 0 Cp5 7 , p6 0 Cp6 6 , p7 0 Cp7 3 , p8 0 Cp8 6 , p9 1 Cp9 6 , p12 0 Cp12 2 , v ref , x in , reset, byte, md0, md1, nmi output voltage a 0 Ca 23 , rd, blw, bhw/p3 3 , cs 0 , d 0 Cd 7 , d 8 /p2 0 Cd 15 /p2 7 , p3 0 , p4 0 Cp4 4 , p5 0 Cp5 7 , p6 0 Cp6 6 , p7 0 Cp7 3 , p8 0 Cp8 6 , p9 1 Cp9 6 , p12 0 Cp12 2 , x out power dissipation operating temperature storage temerature symbol v cc av cc v i v o p d t opr t stg ratings C0.3 to 6.5 C0.3 to 6.5 C0.3 to v cc +0.3 C0.3 to v cc +0.3 300 C20 to 85 C40 to 150 unit v v v v v v v v ma ma ma ma mhz power source voltage analog power source voltage power source voltage analog power source voltage high-level input voltage high-level input voltage low-level input voltage low-level input voltage high-level peak output current high-level average output current low-level peak output current low-level average output current external clock input frequency p2 0 Cp2 7 , p3 0 , p3 3 , p4 0 Cp4 4 , p5 0 Cp5 7 , p6 0 Cp6 6 , p7 0 Cp7 3 , p8 0 Cp8 6 , p9 1 Cp9 6 , p12 0 Cp12 2 , x in , reset, byte, md0, md1, nmi d 0 Cd 7 , d 8 Cd 15 p2 0 Cp2 7 , p3 0 , p3 3 , p4 0 Cp4 4 , p5 0 Cp5 7 , p6 0 Cp6 6 , p7 0 Cp7 3 , p8 0 Cp8 6 , p9 1 Cp9 6 , p12 0 Cp12 2 , x in , reset, byte, md0, md1, nmi d 0 Cd 7 , d 8 Cd 15 a 0 Ca 23 , rd, blw, bhw/p3 3 , cs 0 , d 0 Cd 7 , d 8 /p2 0 Cd 15 /p2 7 , p3 0 , p4 0 Cp4 4 , p5 0 Cp5 7 , p6 0 Cp6 6 , p7 0 Cp7 3 , p8 0 Cp8 6 , p9 1 Cp9 6 , p12 0 Cp12 2 a 0 Ca 23 , rd, blw, bhw/p3 3 , cs 0 , d 0 Cd 7 , d 8 /p2 0 Cd 15 /p2 7 , p3 0 , p4 0 Cp4 4 , p5 0 Cp5 7 , p6 0 Cp6 6 , p7 0 Cp7 3 , p8 0 Cp8 6 , p9 1 Cp9 6 , p12 0 Cp12 2 a 0 Ca 23 , rd, blw, bhw/p3 3 , cs 0 , d 0 Cd 7 , d 8 /p2 0 Cd 15 /p2 7 , p3 0 , p4 0 Cp4 4 , p5 0 Cp5 7 , p6 0 Cp6 6 , p7 0 Cp7 3 , p8 0 Cp8 6 , p9 1 Cp9 6 , p12 0 Cp12 2 a 0 Ca 23 , rd, blw, bhw/p3 3 , cs 0 , d 0 Cd 7 , d 8 /p2 0 Cd 15 /p2 7 , p3 0 , p4 0 Cp4 4 , p5 0 Cp5 7 , p6 0 Cp6 6 , p7 0 Cp7 3 , p8 0 Cp8 6 , p9 1 Cp9 6 , p12 0 Cp12 2 v cc av cc v ss av ss v ih v ih v il v il i oh (peak) i oh (avg) i ol (peak) i ol (avg) f(x in ) notes 1: average output current is the average value of an interval of 100 ms. 2: the sum of i ol(peak) for a 0 Ca 23 , d 0 Cd 7 , d 8 /p2 0 Cd 15 /p2 7 , ports p8 0 Cp8 6 must be 80 ma or less, the sum of i oh(peak) for a 0 Ca 23 , d 0 Cd 7 , d 8 /p2 0 Cd 15 /p2 7 , ports p8 0 Cp8 6 must be 80 ma or less, the sum of i ol(peak) for ports p3 0 , rd, blw, bhw/p3 3 , cs 0 , p4 0 Cp4 4 , p5 0 Cp5 7 , p6 0 Cp6 6 , p7 0 Cp7 3 , p9 1 Cp9 6 , p12 0 Cp12 2 must be 80 ma or less, the sum of i oh(peak) for p3 0 , rd, blw, bhw/p3 3 , cs 0 , p4 0 Cp4 4 , p5 0 Cp5 7 , p6 0 Cp6 6 , p7 0 Cp7 3 , p9 1 Cp9 6 , p12 0 Cp12 2 must be 80 ma or less. 4.5 0.8v cc 0.5v cc 0 0 5.5 v cc v cc 0.2v cc 0.16v cc C10 C5 10 5 20 parameter symbol max. typ. min. limits 5 v cc 0 0 M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers 18 dc electrical characteristics (vcc = 5 v, vss = 0 v, ta = C20 to 85 c, f(x in ) = 20 mhz, unless otherwise noted) parameter high-level output voltage a 0 Ca 23 , cs 0 , d 0 Cd 7 , d 8 /p2 0 Cd 15 /p2 7 , p3 0 , p4 0 Cp4 4 , p5 0 Cp5 7 , p6 0 Cp6 6 , p7 0 Cp7 3 , p8 0 Cp8 6 , p9 1 Cp9 3 , p12 0 Cp12 2 high-level output voltage a 0 Ca 23 , cs 0 , d 0 Cd 7 , d 8 /p2 0 Cd 15 /p2 7 , p4 0 , p4 4 , p9 1 C p9 3 high-level output voltage rd, blw, bhw/p3 3 , p9 4 /cas/w, p9 5 /wrl/lcas, p9 6 /wrh/ucas low-level output voltage a 0 Ca 23 , cs 0 , d 0 Cd 7 , d 8 /p2 0 Cd 15 /p2 7 , p3 0 , p4 0 Cp4 4 , p5 0 Cp5 7 , p6 0 Cp6 6 , p7 0 Cp7 3 , p8 0 Cp8 6 , p9 1 Cp9 3 , p12 0 Cp12 2 low-level output voltage a 0 Ca 23 , cs 0 , d 0 Cd 7 , d 8 /p2 0 Cd 15 /p2 7 , p4 0 , p4 4 , p9 1 C p9 3 low-level output voltage rd, blw, bhw/p3 3 , p9 4 /cas/w, p9 5 /wrl/lcas, p9 6 /wrh/ucas hysteresis ta0 in Cta4 in , tb0 in Ctb2 in , int 0 Cint 4 , dmareq 0 Cdmareq 3 , ad trg , cts 0 , clk 0 , clk 1 , nmi, rdy, hold, rxd 0 , rxd 1 hysteresis reset hysteresis x in high-level input current d 0 Cd 7 , d 8 /p2 0 Cd 15 /p2 7 , p3 0 , p3 3 , p4 0 Cp4 4 , p5 0 Cp5 7 , p6 0 Cp6 6 , p7 0 Cp7 3 , p8 0 Cp8 6 , p9 1 Cp9 6 , p12 0 Cp12 2 , x in , reset, byte, md0, md1, nmi low-level input current d 0 Cd 7 , d 8 /p2 0 Cd 15 /p2 7 , p3 0 , p3 3 , p4 0 Cp4 4 , p5 0 Cp5 7 , p6 0 Cp6 6 , p7 0 Cp7 3 , p8 0 Cp8 6 , p9 1 Cp9 6 , p12 0 Cp12 2 , x in , reset, byte, md0, md1, nmi ram hold voltage power source current unit v v v v v v v v v a a v ma a f(x in ) = 20 mhz. ta = 25 c when clock is stopped. ta = 80 c when clock is stopped. test conditions i oh = C10 ma i oh = C400 a i oh = C10 ma i oh = C400 a i ol = 10 ma i ol = 2 ma i ol = 10 ma i ol = 2 ma v i = 5.0 v v i = 0 v when clock is stoped. symbol v oh v oh v oh v ol v ol v ol v t+ vt C v t+ vt C v t+ vt C i ih i il v ram i cc min. 3 4.7 3.4 4.8 0.4 0.5 0.1 2 limits typ. 25 max. 2 0.45 1.6 0.4 1 1.5 0.3 5 C5 50 1 20 at reset in micro- processor mode, output-only pins are open, and the other pins are con- nected to vss. 19 M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers resolution absolute accuracy ladder resistance conversion time reference voltage analog input voltage r ladder t conv v ref v ia v ref = v cc v ref = v cc v ref = v cc f(x in ) 20 mhz max. a-d converter characteristics (v cc = av cc = 5 v 10 %, v ss = av ss = 0 v, t a = C20 to 85 c, unless otherwise noted) unit parameter symbol test conditions limits min. 10-bit resolution mode 8-bit resolution mode 10-bit resolution mode 8-bit resolution mode 5 5.9 2.45 (note) 2.7 0 10 3 2 v cc v ref bits lsb lsb k w s v v note: this is applied when a-d conversion freguency ( f ad ) = f 1( f ) . M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers 20 t c(ta) t w(tah) t w(tal) f(x in ) 20 mhz f(x in ) 20 mhz f(x in ) 20 mhz peripheral device input/output timing (v cc = 5 v 10 %, v ss = 0 v, t a = C20 to 85 c, f(x in ) = 20 mhz unless otherwise noted) * for limits depending on f(x in ), their calculation formulas are shown below. also, the values at f(x in ) = 20 mhz are shown in ( ). timer a input (up-down input and count input in event counter mode) t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in -up) symbol ta i out input cycle time ta i out input high-level pulse width ta i out input low-level pulse width ta i out input setup time ta i out input hold time parameter limits min. 2000 1000 1000 400 400 max. ns ns ns ns ns unit timer a input (external trigger input in pulse width modulation mode) t w(tah) t w(tal) symbol tai in input high-level pulse width tai in input low-level pulse width parameter min. 80 80 limits max. ns ns unit limits symbol parameter min. max. unit 8 10 9 f(x in ) (400) tai in input cycle time tai in input high-level pulse width tai in input low-level pulse width ns ns ns 80 80 timer a input (external trigger input in one-shot pulse mode) limits symbol parameter min. max. unit 16 10 9 f(x in ) 8 10 9 f(x in ) 8 10 9 f(x in ) (800) (400) (400) t c(ta) t w(tah) t w(tal) ta i in input cycle time ta i in input high-level pulse width ta i in input low-level pulse width ns ns ns timer a input (gating input in timer mode) note : the tai in input cycle time requires 4 or more cycles of a count source. the tai in input high-level pulse width and the tai in input low-level pulse width respectively require 2 or more cycles of a count source. the limits in this table are applied when the count source = f 2 at f(x in ) 20 mhz. timer a input (count input in event counter mode) t c(ta) t w(tah) t w(tal) symbol tai in input cycle time tai in input high-level pulse width tai in input low-level pulse width parameter min. 80 40 40 limits max. ns ns ns unit f(x in ) 20 mhz 21 M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers t c(ta) t su(ta jin -ta jout ) t su(ta jout -ta jin ) symbol parameter min. 800 200 200 limits max. ns ns ns unit timer a input (two-phase pulse input in event counter mode) tai in input cycle time taj in input setup time taj out input setup time t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t h(t in -up) t su(up-t in ) t su(taj in -taj out ) t su(taj out -taj in ) t su(taj in -taj out ) t su(taj out -taj in ) t c(ta) t su(taj out -taj in ) tai in input tai out input (up-down input) ?p-down input and count input in event counter mode ?ating input in timer mode ?ount input in event counter mode ?xternal trigger input in one-shot pulse mode ?xternal trigger input in pulse width modulation mode tai out input (up-down input) tai in input (when count at falling) tai in input (when count at rising) ?wo-phase pulse input in event counter mode taj in input taj out input test conditions ?cc = 5 v 10 %, ta = ?0 to 85 ? ?nput timing voltage : v il = 1.0 v, v ih = 4.0 v M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers 22 f(x in ) 20 mhz f(x in ) 20 mhz f(x in ) 20 mhz f(x in ) 20 mhz f(x in ) 20 mhz f(x in ) 20 mhz t c(tb) t w(tbh) t w(tbl) t c(tb) t w(tbh) t w(tbl) timer b input (count input in event counter mode) symbol tbi in input cycle time (one edge count) tbi in input high-level pulse width (one edge count) tbi in input low-level pulse width (one edge count) tbi in input cycle time (both edge count) tbi in input high-level pulse width (both edge count) tbi in input low-level pulse width (both edge count) parameter limits min. 80 40 40 160 80 80 max. ns ns ns ns ns ns unit limits symbol parameter min. max. unit 16 10 9 f(x in ) 8 10 9 f(x in ) 8 10 9 f(x in ) (800) (400) (400) t c(tb) t w(tbh) t w(tbl) tbi in input cycle time tbi in input high-level pulse width tbi in input low-level pulse width ns ns ns timer b input (pulse period measurement mode) note: the tbi in input cycle time requires 4 or more cycles of a count source. the tbi in input high-level pulse width and the tbi in input low-level pulse width respectively require 2 or more cycles of a count source. the limits in this table are applied when the count source = f 2 at f(x in ) 20 mhz. limits symbol parameter min. max. unit 16 10 9 f(x in ) 8 10 9 f(x in ) 8 10 9 f(x in ) (800) (400) (400) t c(tb) t w(tbh) t w(tbl) tbi in input cycle time tbi in input high-level pulse width tbi in input low-level pulse width ns ns ns timer b input (pulse width measurement mode) note: the tbi in input cycle time requires 4 or more cycles of a count source. the tbi in input high-level pulse width and the tbi in input low-level pulse width respectively require 2 or more cycles of a count source. the limits in this table are applied when the count source = f 2 at f(x in ) 20 mhz. t c(ad) t w(adl) symbol ad trg input cycle time (minimum allowable trigger) ad trg input low-level pulse width parameter min. 1000 125 limits max. ns ns unit a-d trigger input 23 M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers t c(ck) t w(ckh) t w(ckl) t d(c-q) t h(c-q) t su(d-c) t h(c-d) serial i/o symbol clk i input cycle time clk i input high-level pulse width clk i input low-level pulse width t x d i output delay time t x d i hold time r x d i input setup time r x d i input hold time parameter limits min. 200 100 100 0 20 90 max. 80 ns ns ns ns ns ns ns unit t w(inh) t w(inl) symbol int i input/nmi input high-level pulse width int i input/nmi input low-level pulse width parameter min. 250 250 limits max. ns ns unit external interrupt (int i ) input, nmi input t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t su(d-c) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c-q) t h(c-d) t h(c-q) tbi in input ad trg input int i input nmi input clk i input txd i output rxd i input test conditions ?cc = 5 v 10 %, ta = ?0 to 85 ? ?nput timing voltage : v il = 1.0 v, v ih = 4.0 v ?utput timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 50 pf M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers 24 t d( f 1-hldal) t d(rdh-hldal) t d(bxwh-hldal) t pxz(hldal-rdz) t pxz(hldal-bxwz) t pxz(hldal-csiz) t pxz(hldal-alez) t pxz(hldal-az) t pzx(hldal-rdz) t pzx(hldal-bxwz) t pzx(hldal-csiz) t pzx(hldal-alez) t pzx(hldal-az) ready, hold timing timing requirements (v cc = 5 v 10 %, v ss = 0 v, t a = C20 to 85 c, f(x in ) = 20 mhz, unless otherwise noted) t su(rdy- f 1) t su(hold- f 1) t h( f 1-rdy) t h( f 1-hold) symbol rdy input setup time hold input setup time rdy input hold time hold input hold time parameter limits min. 40 40 0 0 max. ns ns ns ns unit switching characteristics (v cc = 5 v 10 %, v ss = 0 v, t a = C20 to 85 c, f(x in ) = 20 mhz, unless otherwise noted) symbol hlda output delay time hlda low-level output delay time after read hlda low-level output delay time after write floating start delay time floating start delay time floating start delay time floating start delay time floating start delay time floating release delay time floating release delay time floating release delay time floating release delay time floating release delay time parameter min. tc C15 (note) tc C15 (note) C15 C15 C15 C15 C15 0 0 0 0 0 limits max. 20 10 10 10 10 10 ns ns ns ns ns ns ns ns ns ns ns ns ns unit note: tc = 1/f(x in ). 25 M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers test conditions ?cc = 5 v 10 %, ta = ?0 to 85 ? ?dy input, hold input : v il = 1.0 v, v ih = 4.0 v ?lda output : v ol = 0.8 v, v oh = 2.0 v, c l = 50 pf aaaa f 1 rdy input t su(rdy- f 1 ) rd blw bhw aaa : wait inserted by software (the above is applied when 1 wait is selected.) : wait inserted by ready function rdy input t h( f 1 -rdy) f 1 hold input t su(hold- f 1 ) t d( f 1 -hldal) t pxz(hldal-rdz) t pxz(hldal-bxwz) t pxz(hldal-csiz) t pxz(hldal-az) t h( f 1 -hold) t d( f 1 -hldal) t pzx(hldal-rdz) t pzx(hldal-bxwz) t pzx(hldal-csiz) t pzx(hldal-alez) t pzx(hldal-az) hi-z hi-z hi-z hi-z hi-z hold input hlda output rd blw bhw cs i a 0 ? 23 output t d(rdh-hldal) t d(bxwh-hldal) t pxz(hldal-alez) ale M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers 26 when ale expansion wait is selected w = 0 (0 wait) w = 1 (1 wait) w = 2 (2 wait) tc = 1/f(x in ). external bus timing for limits depending on f(x in ), their calculation formulas are shown below. external clock input t r t f t w(l) t w(h) t w(half) f(x in ) t c test conditions ?cc = 5 v 10 %, ta = ?0 to 85 ? ?nput timing voltage : v il = 1.0 v, v ih = 4.0 v (t w(h) , t w(l) , t r , t f ) ?nput timing voltage : 2.5 v (t c , t w(half) ) timing requirements (v cc = 5 v 10 %, v ss = 0 v, t a = C20 to 85 c, f(x in ) = 20 mhz, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns ns ns ns 50 0.45tc 0.5tc C 8 0.5tc C 8 15 0 0 0.55tc 8 8 (2 + w)tc C 45 (1.5 + w)tc C 35 (1 + w)tc C 30 (1 + w)tc C 35 50 0.45tc 0.5tc C 8 0.5tc C 8 15 0 0 limits external clock input cycle time external clock input pulse width with half input-volage external clock input high-level pulse width external clock input low-level pulse width external clock input rise time external clock input fall time address access time chip select access time read access time read data setup time data input hold time after read address access time at burst rom access data hold time after address at burst rom access parameter max. min. t c t w(half) t w(h) t w(l) t r t f t a(a-d) t a(csil-d) t a(rdl-d) t su(d-rdl) t h(rdh-d) t a(ba-d) t h(ba-d) unit symbol max. min. when 0/1/2 wait is selected 0.55tc 8 8 4tc C 45 3.5tc C 35 2tc C 30 2tc C 35 27 M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers switching characteristics (v cc = 5 v 10 %, v ss = 0 v, t a = C20 to 85 c, f(x in ) = 20 mhz, unless otherwise noted) 15 10 15 10 0.5tc + 10 read low-level output delay time read high-level output delay time write low-level output delay time write high-level output delay time ale pulse width ale completion delay time after address stabilization read output pulse width read output high-level width (note 1) write disable valid time after read (note 2) address valid time before read address hold time after read (note 3) ale completion delay time after read start read disable valid time after ale completion chip select valid time before read chip select output valid time before read completion chip select hold time after read next write cycle data output delay time after read (note 2) write output pulse width write output high-level width (note 1) read disable valid time after write (note 2) address valid time before write address hold time after write (note 3) ale completion delay time after write start write disable valid time after ale completion chip select valid time before write chip select output valid time before write completion chip select hold time after write data output valid time before write completion data hold time after write floating start delay time after write C10 C10 C10 C10 tc C 20 1.5tc C 30 2tc C 15 2tc C 15 tc C 15 2tc C 30 8 0.5tc C 20 1.5tc C 20 3.5tc C 20 0.5tc C 20 tc C 15 2tc C 15 2tc C 15 tc C 15 2tc-30 8 0.5tc C 20 1.5tc C 20 3.5tc C 20 0.5tc C 20 2tc C 20 0.5tc C 10 15 10 15 10 20 20 0.5tc + 10 C10 C10 C10 C10 0.5tc C 20 tc C 30 (1 + w)tc C 15 tc C 15 tc C 15 tc C 30 8 0.5tc C 20 (1.5 + w)tc C 20 0.5tc C 20 tc C 15 (1 + w)tc C 15 tc C 15 tc C 15 tc C 30 8 0.5tc C 20 (1.5 + w)tc C 20 0.5tc C 20 (1 + w)tc C 20 0.5tc C 10 t d( f 1-rdl) t d( f 1-rdh) t d( f 1-bxwl) t d( f 1-bxwh) t w(aleh) t d(a-alel) t w(rdl) t w(rdh) t d(rdh-bxwh) t d(a-rdh) t h(rdh-a) t d(rdh-alel) t d(alel-rdh) t d(csil-rdh) t d(csil-rdl) t h(rdh-csil) t d(rdh-d) t w(bxwl) t w(bxwh) t d(bxwh-rdh) t d(a-bxwh) t h(bxwh-a) t d(bxwh-alel) t d(alel-bxwh) t d(csil-bxwh) t d(csil-bxwl) t h(bxwh-csil) t d(d-bxwl) t h(bxwh-d) t pxz(bxwh-dz) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns parameter max. min. unit symbol limits max. min. when 0/1/2 wait is selected when ale expansion wait is selected notes 1: when the bus cycle just before this parameter is for the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns). 2: when accessing the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns). 3: when accessing the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns). however, except for the case at instruction prefetch. M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers 28 test conditions ?cc = 5 v 10 %, ta = ?0 to 85 ? ?nput timing voltage : v il = 0.8 v, v ih = 2.5 v ?utput timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 15 pf (cs i ) ?utput timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 50 pf (except for cs i ) bus cycle 29 M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers bus cycle t d(csil-bxwl) t d(csil-rdl) t d(a-alel) t h(rdh-d) t h(rdh-a) t h(rdh-csil) t w(rdl) t a(csil-d) t a(rdl-d) t a(a-d) t d(a-rdh) t d(csil-rdh) t su(d-rdl) t w(aleh) t d(rdh-bxwh) t c M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers 30 burst rom access : 0/1/2 wait at instruction prefetch t h(ba-d) t d(rdh-bxwh) blw bhw d 0 ? 7 , d 8 ? 15 rd t a(rdl-d) t d(a-rdh) cs i t h(rdh-a) t a(csil-d) t a(a-d) t a(ba-d) a 0 ? 23 t h(ba-d) t h(ba-d) t h(rdh-d) t a(ba-d) t a(ba-d) t h(rdh-csil) t d(csil-rdh) t d(a-alel) t w(aleh) ale t d(rdh-alel) t w(rdh) test conditions ?cc = 5 v 10 %, ta = ?0 to 85 ? ?nput timing voltage : v il = 0.8 v, v ih = 2.5 v ?utput timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 15 pf (cs i ) ?utput timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 50 pf (except for cs i ) 31 M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers t w(rash) t d(cash-rash) t h(rasl-cash) t h(casl-rasl) t w(casl) t d(ra-rash) t h(rasl-ra) t d(ca-cash) t h(cash-ca) t d(wh-cash) t d(wl-cash) t h(casl-wl) t d(d-cash) t h(casl-d) t pxz(cash-d) t d(caf-cash) t d(wfl-cash) t d(df-cash) t pxz(wh-d) t a(rasl-d) t a(casl-d) t h(cash-d) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.5tc C 20 1.5tc C 20 1.5tc C 20 tc C 15 tc C 15 0.5tc C 25 tc C 40 0.5tc C 20 0 3tc C 15 tc C 15 tc C 15 tc C 20 1.5tc C 15 0.5tc + 10 tc C 40 0.5tc C 20 0.5tc C 20 dram access timing requirements (v cc = 5 v 10 %, v ss = 0 v, t a = 0 to 70 c, f(x in ) = 20 mhz, unless otherwise noted) limits ras access time cas access time data input hold time after cas parameter max. min. unit symbol ns ns ns 0 2.5tc C 35 tc C 30 limits ras high-level pulse width cas high-level valid time before ras cas high-level hold time after rass low level ras hold time after cass low level cas low-level pulse width row address valid time before ras row address hold time after rass low level column address valid time before cas column address hold time after cass high level w high-level valid time before cas w low-level valid time before cas w hold time after cass low level data output valid time before cas data output hold time after cass low level floating start delay time after cas column address valid time before cas (when fast page access on is selected) w low-level valid time before cas (when fast page access on is selected) data output valid time before cas (when fast page access on is selected) floating start delay time after write parameter max. min. unit symbol switching characteristics (v cc = 5 v 10 %, v ss = 0 v, t a = 0 to 70 c, f(x in ) = 20 mhz, unless otherwise noted) 0.5tc + 10 M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers 32 t h(rasl-ra) dram access : fast page access = off f 1 d 0 ? 7 , d 8 ? 15 ras i a 0 ? 23 lcas,ucas (cas) w (wrl,wrh) column address t h(casl-rasl) t a(casl-d) t h(cash-d) t w(rash) w (wrl,wrh) d 0 ? 7 , d 8 ? 15 ras i a 0 ? 23 t d(ra-rash) t h(cash-ca) t w(casl) t d(wh-cash) t a(rasl-d) lcas,ucas (cas) t h(rasl-ra) t d(ca-cash) t d(cash-rash) row address column address row address t h(rasl-cash) t h(casl-d) t w(rash) t d(ra-rash) t h(cash-ca) t w(casl) t d(d-cash) 33 M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers t d(ra-rash) dram access : fast page access = on t a(casl-d) t h(cash-d) t w(rash) t w(casl) t d(ra-rash) t h(cash-ca) t d(wh-cash) t a(rasl-d) t w(casl) t w(casl) t h(cash-ca) t h(rasl-ra) t d(ca-cash) t d(caf-cash) t d(caf-cash) t h(cash-ca) t a(casl-d) t h(cash-d) t d(cash-rash) t a(casl-d) t h(cash-d) t h(casl-rasl) t h(rasl-cash) row address column address column address column address t pxz(wh-d) t w(rash) t h(cash-ca) t w(casl) t w(casl) t w(casl) t h(cash-ca) t h(rasl-ra) t d(ca-cash) t d(caf-cash) t d(caf-cash) t h(cash-ca) t d(cash-rash) t h(casl-d) t d(d-cash) t d(wl-cash) t h(casl-d) t d(df-cash) t d(wfl-cash) t h(casl-wl) t h(casl-d) t d(df-cash) t d(wfl-cash) t h(casl-wl) t h(casl-rasl) t h(rasl-cash) row address column address column address column address t h(casl-wl) f 1 w (wrl,wrh) rasi a 0 ? 23 lcas,ucas (cas) M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers 34 t w(ras cbr l) t w(cas cbr l) t d(cas cbr l-ras cbr h) t d(ras cbr l-cas cbr l) t d(cas slfr l-ras slfr h) t h(ras slfr h-cas slfr l) 2tc C 15 2tc C 15 tc C 15 tc C 15 tc C 15 C15 ns ns ns ns ns ns dram refresh switching characteristics (v cc = 5 v 10 %, v ss = 0 v, t a = 0 to 70 c, f(x in ) = 20 mhz, unless otherwise noted) limits ras low-level pulse width (at cas before ras refresh) cas low-level pulse width (at cas before ras refresh) ras high-level valid time after cass low level start (at cas before ras refresh) cas low-level valid time after rass low level start (at cas before ras refresh) ras high-level valid time after cass low level start (at self refresh) cas low-level hold time after rass high level (at self refresh) parameter max. min. unit symbol 15 35 M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers t d(cas cbr l-ras cbr h) dram refresh : cas before ras refresh t d(ras cbr l-cas cbr l) t w(ras cbr l) t w(cas cbr l) refresh cycle t d(cas slfr l-ras slfr h) t h(ras slfr h-cas slfr l) refresh cycle dram refresh : self refresh f 1 w (wrl,wrh) ras i lcas,ucas (cas) f 1 w (wrl,wrh) ras i lcas,ucas (cas) test conditions ?cc = 5 v 10 %, ta = 0 to 70 ? ?utput timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 15 pf (ras i ) ?utput timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 50 pf (except for ras i ) M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers 36 t w(tcl) t d(rdh-tcl) t d(bxwh-tcl) t d(tcl-dmaackl) unit tc input setup time tc input pulse width dmareq i input setup time dmareq i input pulse width dma transfer timing timing requirements (v cc = 5 v 10 %, v ss = 0 v, t a = C20 to 85 c, f(x in ) = 20 mhz, unless otherwise noted) max. parameter symbol unit min. limits t su(tc in l- f 1) t w(tc in l) t su(drql- f 1) t w(drql) ns ns ns ns 40 tc + 20 40 tc tc output pulse width tc output start delay time after read tc output start delay time after write dmaack low-level output valid time after tc output start switching characteristics (v cc = 5 v 10 %, v ss = 0 v, t a = C20 to 85 c, f(x in ) = 20 mhz, unless otherwise noted) max. parameter symbol min. limits ns ns ns ns tc C 20 tc C 15 tc C 15 2.5tc C 20 tc 50 pf 3 k w test circuit for tc output 37 M37920S4CGP preliminary notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers l tc input f 1 tc input t su(tc in l- f 1 ) l dmareq i input dmareq i input t su(drql- f 1 ) t w(drql) t w(tc in l) f 1 test conditions ?cc = 5 v 10 %, ta = ?0 to 85 ? ?nput timing voltage : v il = 1.0 v, v ih = 4.0 v ?utput timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 50 pf cs i a 0 ? 23 d 0 ? 7 , d 8 ? 15 rd blw bhw ale t w(tcl) tc dmaack i t d(rdh-tcl) t d(bxwh-tcl) t d(tcl-dmaackl) final tranfer cycle terminate processing (next bus cycle) l transfer terminate timing test conditions ?cc = 5 v 10 %, ta = ?0 to 85 ? ?utput timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 50 pf M37920S4CGP preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers notes regarding these materials these materials are intended as a reference to assist our cu stomers in the selection of the mitsubishi semiconductor pro duct be st suited to the customer ? s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility fo r any damage, or infringement of any third-party ? s rights, originat ing in the use of any product data, diagrams, charts or circ uit application examples contained in these materials. all information contained in these materials, including prod uct data, diagrams and charts, represent information on prod ucts at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improveme nts or other reasons. it is therefore recommended that custo mers co ntact mitsubishi electric corporation or an authorized mitsu bishi semiconductor product distributor for the latest product information befor e purchasing a product listed herein. the information described here may contain technical inaccur acies or typographical errors. mitsubishi electric corporati on assu mes no responsibility for any damage, liability or other los s rising from these inaccuracies or errors. mitsubishi electric corporation semiconductors are not desig ned or manufactured for use in a device or system that is us ed unde r circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use o f a pro duct contained herein for any specific purposes, such as app aratus or systems for transportation, vehicular, medical, aerospace, nuclear, or u ndersea repeater use. the prior written approval of mitsubishi electric corporatio n is necessary to reprint or reproduce in whole or in part t hese ma terials. if these products or technologies are subject to the japanes e export control restrictions, they must be exported under a licens e from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control law s and regulations of japan and/or the country of destination is pro hibited. please contact mitsubishi electric corporation or an authori zed mitsubishi semiconductor product distributor for further detail s on these materials or the products contained therein. ? 1999 mitsubishi electric corp. new publication, effective sep. 1999. specifications subject to change without notice. keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when m aking y our circuit designs, with appropriate measures such as (i) p lacement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mish ap. qfp100-p-1420-0.65 1.58 w eight(g) e jedec code eiaj package code lead material alloy 42 100p6s-a plastic 100pin 14 5 20mm body qfp e 0.1 e ee 0.2 e e ee e e e e e symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.35 e e i 2 1.3 e e m d 14.6 e e m e 20.6 10 0 0.1 1.4 0.8 0.6 0.4 23.1 22.8 22.5 17.1 16.8 16.5 0.65 20.2 20.0 19.8 14.2 14.0 13.8 0.2 0.15 0.13 0.4 0.3 0.25 2.8 0 3.05 e e e e c h e 1 30 31 81 50 80 51 h d d m d m e a f b a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f 100 p ackage outline rev. rev. no. date 1.00 first edition 990916 revision description list M37920S4CGP datasheet (1/1) revision description |
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